FIG. 1 shows a block diagram of a circuit 10 illustrating a conventional PLL system. The circuit 10 generally comprises a receive circuit 12 and a transmit circuit 14. The transmit circuit 14 generally comprises a number of outputs 16a-16n that may present information (i.e., serial data) about a number of ports Port1-PortN. The receive circuit 12 may have a number of inputs 18a-18n that may receive the information from the transmitter circuit 14. The receive circuit 12 generally comprises a deserializer circuit 20, a receive PLL 22 and a selectable multiplexer 24. The selectable multiplexer 24 presents a signal to the receive PLL in response to the information received at the inputs 18a-18n. The receive PLL presents a first signal to an input 26 of the deserializer 20 and a second signal to an input 28 of the deserializer 20. The deserializer 20 may present a parallel data word at an output 30 in response to the signals received at the inputs 26 and 28.
The transmitter circuit 14 generally comprises a divide circuit 40, a transmit PLL 42, a serializer circuit 44 and a selectable demultiplexer 46. The serializer 44 generally receives a parallel data word at an input 50 and a signal BIT_CLOCK at an input 52. The serializer 44 generally presents a signal to an input 54 in response to the parallel data received at the input 50 and the bit clock received at the input 52. The transmit PLL 42 generally presents the signal BIT_CLOCK in response to a reference clock signal REFCLK received at an input 56 and a signal BYTE_CLOCK received at an input 58. The divide circuit 40 generally converts the signal BIT_CLOCK to the signal BYTE_CLOCK. Data is received by the transmitter circuit 14 on a parallel bus and is serialized using the signal BIT_CLOCK. Once the data is serialized, the data is sent through the selectable demultiplexer 46 to one of the ports Port1-PortN.
For the receive side, the data received by one of the ports Port1-PortN of the receive circuit 12. The data is passed through the selectable multiplexer 24 to the receive PLL 22. The receive PLL 22 recovers a clock signal from the incoming serial data, and presents the serial data and the recovered clock to the inputs 26 and 28 of the deserializer circuit 20. The deserializer circuit 20 presents the parallel data at the output 30. The circuit 10 has two PLLs (i.e., the receive PLL 22 and the transmit PLL 42) one for the receive circuit 12 and one for the transmit circuit 14.